--- Log opened Thu Dec 08 00:00:32 2016
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07:06 < kanzure> thesnark: welcome back
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07:53 < wrldpc1> Sorry about that :(
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09:27 < kanzure> hrm.
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09:35 < nmz787_w> mm hm, mm hm, mm hm, mm hm
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09:42 < chris_99> heh.  Are you using FPGAs did you say the other day nmz787_w?
09:42 < kanzure> nmz787_w: https://youtu.be/2YCHmOAbJBs
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11:19 < nmz787_w1> chris_99: no I'm not using FPGAs, but I'm reading a bunch of SystemVerilog lately, but it's mostly test-bench stuff, but I guess being comfortable with basic syntax is a plus for any verilog I guess I might do in the future if I were to get into FPGAs
11:19 < chris_99> aha gotcha, i'm hoping to possibly get the digilent zybo soon, if i can find some cash
11:20 < chris_99> as i want to play with generating hdmi sigs
11:20 < nmz787_w1> I have the DE0-nano
11:20 < nmz787_w1> ah
11:20 < chris_99> ohh yeah that board looks good
11:20 < chris_99> i want to make some silly game or something heh
11:21 < nmz787_w1> I think I got it for like $60 with the academic discount years ago
11:21 < chris_99> possibly with a very simplistic softcore
11:21 < chris_99> oh nice
11:22 < nmz787_w1> I do have plans to learn enough Verilog to implement some unit tests for this project I'm working with now
11:22 < kanzure> good
11:23 < chris_99> cool, i'm not sure what to learn, either vhdl or verilog or..
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11:28 < kanzure> both
11:28 < nmz787_w1> chris_99: I'd start with MyHDL in Python
11:28 < chris_99> i'm not sure what that is, i'll have a looky
11:28 < nmz787_w1> and then play with the converters, it can emit VHDL and Verilog
11:30 < chris_99> hmm
11:30 < nmz787_w1> there doesn't seem to be anything special with these built-for-HDL languages, other than another syntax to learn... the only real specialty I guess would be that they're industry borne and the industry pays them to modify the software to be very up to date...
11:30 < chris_99> would vhdl/verilog be more powerful though, if it's translating to that
11:30 < nmz787_w1> I don't know how horrible Verilog is in general at a compiler level, but I bet it's version and environment hell
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11:33 < nmz787_w1> chris_99: presumably, but at the same time, presumably you aren't big-industry.... aren't doing cutting edge IPs that require cutting edge silicon processes...
11:33 < chris_99> hehe
11:33 < chris_99> this is true
11:34 < nmz787_w1> chris_99: also many of those greater powers are more costly licensing addons
11:35 < chris_99> gotcha
11:37 < chris_99> http://www.lowrisc.org/ seen that?
11:38 < chris_99> i was linked to it recently, i think they've got a verilog implementation iirc
11:38 < nmz787_w1> ah, RISC-V, yeah I've read a little on that before
11:39 < nmz787_w1> I've been working on enabling interactive usage of HDL simulations, because emulating with an FPGA is more complicated, even though its faster
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11:41 < chris_99> simulating them one a cpu you mean?
11:42 < nmz787_w1> yeah, linux compiler/simulator
11:42 < nmz787_w1> edaplayground.com has a lot of options to select from to check out the different backends
11:43 < nmz787_w1> they even have the commercial ones
11:43 < nmz787_w1> (but you agree when you sign in with your Google account to not use them for commercial work)
11:43 < chris_99> oooh
11:44 < chris_99> i'd not seen that before
11:45 < nmz787_w1> they even have some of the more complex test bench stuff, OVM/UVM (I think they only have examples for UVM actually, but I think it has some similarities since it was a next-gen evolution thing)
11:45 < nmz787_w1> (I am dealing with trying to learn OVM, since it is used a lot here)
11:46 < chris_99> OVM?
11:46 < nmz787_w1> ummm
11:47 < nmz787_w1> Open Verification Methodology
11:47 < nmz787_w1> it's just a library
11:47 < nmz787_w1> with a big set of best-known practices
11:48 < nmz787_w1> it is pretty mind boggling
11:48 < chris_99> oh interesting, it somehow verifies the verilog for 'correctness'?
11:49 < kanzure> correctness is v. important
11:49 < kanzure> theorem provers + verilog stuff
11:49 < kanzure> you can't test all possible states, you have to do proof stuff instead
11:50 < nmz787_w1> basically, my ultra dumb understanding and one-liner response might be: it has random number/bit/bit-list generators, that get injected into any wires that are exposed in your HDL part... and a bunch of API on top of that to make it less bug-prone
11:50 < chris_99> that sounds very complex, how does it know if the verilog is correct, as it can't know your intentions?
11:50 < nmz787_w1> and then you can override random behaviour and drive structured data
11:50 < chris_99> hmm is that like fuzzing you mean?
11:50 < nmz787_w1> i.e. instead of random data into a serial port, start sending packets of bits with real info in them
11:51 < nmz787_w1> sort of, I guess, from what I can tell
11:51 < chris_99> interesting
11:52 < nmz787_w1> like it will randomly fuzz, and tell you if your HDL goes wonky, or fails some assertion (like during random testing the memory bits should remain intact, because I have asserted the write-protect bit is ON and can't change during the test)
11:52 < nmz787_w1> idk at what end of proof vs all-permutations it executes at
11:53 < nmz787_w1> but there are definitely API hooks to connect to such formal verification techniques
11:54 < chris_99> ahh
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16:28 < kanzure> bloop
16:29 < cluckj> beep
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16:37 < nmz787_w> sploink
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17:14 < docl> https://www.youtube.com/watch?v=b04X0xsdjLg
17:16 < kanzure> .title
17:16 < yoleaux> RI Seminar: Gregory S. Chirikjian : Stochastic Models in Robotics - YouTube
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18:14 < anachronick> http://time.com/time-person-of-the-year-2016-crispr-runner-up/
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18:17 < kanzure> .to CaptHindsight do you know someone who would print rolls of custom stickers?
18:17 < yoleaux> kanzure: I'll pass your message to CaptHindsight.
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21:10 < nmz787_w> .tell kanzure is .to the new .tell ?
21:10 < yoleaux> nmz787_w: I'll pass your message to kanzure.
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23:08 < JayDugger> Good morning.
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--- Log closed Fri Dec 09 00:00:33 2016