--- Log opened Thu Jan 13 00:00:28 2022
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02:51 < juri_> eeew, rust. :)
04:02 < L29Ah> maaku: so was it aggressive violence or notification of retaliation in case of attack?
05:02 < maaku> L29Ah: requiring people to get a medically tested and proven safe vaccine is not an "attack" from any reasonable perspective
05:02 < maaku> but we are way off topic
05:04 < lsneff> maaku: because the current ones are bad
05:12 < maaku> lsneff: then say you will conduct civil disobediance and nonviolently refuse to take the vaccine
05:13 < maaku> don't say that you will shoot dead any government worker who is merely doing their job, then <surpised pikachu face> when you get banned from twitter
05:19 < lsneff> Qua?
05:19 < lsneff> Huh?
05:37 < nsh> (not that i advocate this in the current context but the correct strategy at the point of mandate if one were adamant to exercise their right to refuse a medical procedure is not unilateral noncompliance but a dialectic of conditionality)
05:43 < nsh> (that is one makes a proposal of under what conditions they would be satisfied that they must acquiesce to the treatment, e.g. it being established that X,Y,Z and expects a counterproposal which would reduce to what provisions normally afforded by the counterparty (in this case the civic society) might be made conditional on voluntary compliance, e.g. access to public fora, utilities, employments in the public sector or under civic guarantorship. premature 
05:43 < nsh> outright civic disobedience prior to the threshold at which enforcement at scale becomes inviable makes violent coercion an inevitability and forecloses on the discourse of compromise.)
05:45 < nsh> or from a simpler analysis it's just a good tactic to drag out the use of the stick procedurally until it's no longer as useful as it was at the point of crisis
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07:16 < lsneff> maaku: oh I was talking about the HdL
07:16 < lsneff> Not vaccines
07:16 < lsneff> The current ones are good
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09:38 < maaku> lsneff: in what way do current HDLs suck? I thought clash and chisel were pretty decent
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10:16 < lsneff> I think the level of abstraction is wrong
10:16 < lsneff> They’re too low-level
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10:23 < nmz787> lsneff: I just had an EE job candidate tell me verilog was the first programming language that clicked fo rher
10:24 < nmz787> and that when she started using it she really enjoyed it compared to the few other languages she'd been exposed to (Assembly, C, Matlab)
10:24 < nmz787> vs it took me like 10 years of hobby interested to finally be able to code something half-decent in verilog and that was just like some timer and blinking LED stuff
10:27 < lsneff> Well, I'm not surprised that someone liked verilog more than C or matlab
10:28 < lsneff> Verilog is great in that it's very explicit, but it's still at the wrong level of abstraction.
10:28 < lsneff> It's possible to describe hardware just as explicitly at a slightly higher, dataflow level
10:30 < lsneff> Also, it's just a sucky language that takes too much from C. Sum types, generics, etc would all be very useful for hardware
10:44 < muurkha> aye
10:44 < muurkha> but chisel?
10:46 < lsneff> All the verbosity of embedding within another language and similar level of abstraction to verilog
10:59 < lsneff> Looking at it again, chisel looks like a slightly higher level than verilog, but still too low level in my opinion
11:08 < nmz787> lsneff: maybe you assume too much about the general state of programs written by EEs
11:09 < nmz787> (they're usually terrible and lack any sort of OO structure)
11:09 < nmz787> Verilog is very similar to truth tables and what goes on in a circuits analysis exercise 
11:10 < nmz787> .wik dude
11:10 < saxo> "Dude is English slang (originally American English) for an individual, typically male. From the 1870s to the 1960s, dude primarily meant a person who dressed in an extremely fashionable manner (a dandy) or a conspicuous citified person who was visiting a rural location, a [...]" - https://en.wikipedia.org/wiki/Dude
11:10 < lsneff> Yeah, I probably do assume too much
11:10  * nmz787 decides if I should include "dude" in my property's name
11:10 < lsneff> But I don’t think I expect too much
11:10 < nmz787> lol
11:11 < nmz787> I've learned not to expect much in terms of program elegance from EEs
11:11 < juri_> hey. I can EE, and haskell. :)
11:12 < nmz787> well, but you've been committed to programming for a while AFAIK
11:12 < nmz787> you jumped the fence, lol
11:13 < lsneff> Programmers are expected to write robust, maintainable code
11:13 < nmz787> lololol
11:13 < nmz787> wrong
11:13 < nmz787> they're expected to meet schedules/deadlines
11:13 < lsneff> Why aren’t vlsi designers expected to write robust, maintainable hardware description?
11:13 < nmz787> well
11:13 < juri_> lsneff: go work for a startup for a while. :)
11:13 < lsneff> How so?
11:14 < lsneff> I have, several
11:14 < nmz787> programs do stuff, you can always rewrite them later, maintenance isn't very important for "hardware" projects
11:15 < muurkha> verification and debugging are tho
11:15 < nmz787> unfortunately it's a management thing
11:15 < lsneff> You can reflash FPGAs again
11:15 < lsneff> It is a management and mindset thing
11:15 < nmz787> a manager only has so much expertise, and if they're focusing on the Analog IP meeting design spec, whatever works to get the hardware verified, doesn't really matter to them, unfortunately
11:16 < nmz787> "who cares what database we use, and how the tables are formatted"
11:16 < nmz787> that is a multi-year, maybe decades long theme, in the last group I was in
11:17 < nmz787> yet the IT maintenance and interaction/support, data access models, data formats, analysis pipelines, all depend on normalized data
11:17 < nmz787> but a spec on a data table isn't Verilog design work, isn't analog validation work, isn't probing chips/boards in a lab
11:18 < lsneff> That’s what happens when you have a manager without an engineering background
11:19 < nmz787> not at all
11:19 < nmz787> these are all veteran HARDWARE engineers
11:19 < nmz787> people that can design switch mode power supplies running at hundred of MHz
11:19 < nmz787> people that are analog wizards
11:19 < lsneff> I see
11:20 < nmz787> who cares if they use "software" that consists of excel macros to the capacity that excel offers? they ensure signal integrity
11:20 < nmz787> they ensure no power brown outs
11:20 < nmz787> they ensure industry leading power and performance
11:21 < lsneff> That mindset is why tooling and ease of use of hardware is decades behind software
11:21 < nmz787> they don't care if you have a list of subtasks and GOTO statements, or functions and loops, or classes, or stupidly ridiculous EVERYONE HATES THAT STUPID OVERZEALOUS COMPUTER SCIENCE POMPOUS TEAM WHO USES INFINITELY DEEP CLASS INHERITANCE
11:22 < nmz787> when your CPU company is 100k plus employees... good luck working out the management issues in your lifetime (but if you can, be prepared to be well rewarded)
11:23 < nmz787> working in industry has been immensely enlightening about world politics and why "shit is still broken in the modern world"
11:23 < nmz787> scaling communication channels is really hard
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11:28 < nmz787> if you really want to replace verilog, you should be prepared to become a verilog/systemverilog expert... so that you can inspire professional confidence and slowly evolve industrial methodologies without disrupting revenue streams.
11:29 < nmz787> otherwise your project might end up just being a niche use item, which might satisfy you... or it might just end up "another interesting github experimental project"... or maybe you publish some academic papers on it and inspire some folks later on
11:29 < nmz787> IMO
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11:35 < lsneff> I don’t really want to replace verilog. I just find this quite interesting.
11:36 < lsneff> And I am trying to get experience in hardware
11:36 < nmz787> I know there's been a bunch of these projects in the past decade, pyHDL, then a few more with less hardware-ish and less memorable names that I'm failing to recall
11:37 < nmz787> whitequark did a bunch of good work on one
11:37 < nmz787> they could definitely be part of a new generation of IP design suppliers
11:38 < nmz787> and if you went on to support hardware folks, or be an IP designer yourself, you probably would have some leverage on what tech stack you wanted to use, especially if it was whiz-bang OMG more efficient or readable/maintainable
11:38 < lsneff> I’ve talked to whitequark a bunch about nmigen
11:38 < nmz787> yeah that's the newer one
11:38 < nmz787> migen came before that
11:39 < nmz787> and I still can't remember the other one I played with
11:39 < nmz787> also Python
11:44 < nmz787> this one https://github.com/cfelton/rhea
11:44 < nmz787> what a terrible name for me
11:45 < lsneff> Yeah, MyHDL lmao
11:45 < nmz787> looks like the core is still being developed https://github.com/myhdl/myhdl
11:46 < nmz787> EEs "get" Python... and their terrible Python can be pretty easily supported/massaged by better programmers
11:46 < nmz787> slower processing speed of python is trumped by savings in readability and maintainability between pre-SI and post-SI engineers
11:47 < nmz787> (which are either different companies, or nearly so)
11:48 < nmz787> when you SoC data sheet is a few thousand pages long, using Python is pretty much the logical choice for implementing a hardware validation platform
11:49 < lsneff> python is fine for testbenches, ya
11:50 < nmz787> having your HDL and testbench written in same env is a major win too tho, is my point
11:50 < nmz787> last project I worked on was Python interface for systemverilog testbenches, so post-Si engineers could interact with simulations as if they were real DUTs
11:51 < nmz787> trying to get pre-Si validation engineers to just write their test content in python was a management brick wall
11:51 < nmz787> so they kept relying on stupid conversion scripts, manual rewrite of test content
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13:27 < kanzure> "The kidney was obtained from a genetically engineered pig hundreds of miles away and transplanted into a deceased donor. The donor was maintained on a ventilator, with the consent of the family, for 54 hours while doctors studied the kidney’s function and watched for signs of rejection."
13:58 < maaku> lsneff: clash is haskell. sounds like what you're looking for tbh
14:00 < maaku> I'm not trying to fight this, but I was curious if there was some aspect of the problem space I was missing
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14:10 < fltrz> kanzure: seems like archiveteam has nothing to do with internet archive? I asked and they suggested emailing info@archive.org, which I did before asking here, and later at #archiveteam... still no reply though
14:12 < fltrz> just need to find out where I can find lurking on IRC someone working at internet archive; so I can explain the importance and then they can notify the colleagues
14:19 < nmz787> isn't email the granddaddy of IRC?
15:03 < kanzure> fltrz: jscott@archive.org jefferson@archive.org
15:03 < kanzure> i thought jason scott was archiveteam?
15:17 < fltrz> kanzure: where did you find those email adresses? or they are acquaintances in some sense or another?
15:26 < nmz787> possibly articles like this https://news.ycombinator.com/item?id=15928685
17:45 < kanzure> fltrz: previous correspondence
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--- Log closed Fri Jan 14 00:00:29 2022