--- Log opened Mon May 06 00:00:47 2024
01:01 < hprmbridge> harmoniq.punk> But things have changed in the last 5y. There is a huge amount openness including eda tools. Especially in digital designs. It will increase. Otherwise tech scene will get grimmer and grimmer.
01:03 < fenn> it was a while ago, but last i checked there was only one FPGA series with an open source toolchain, the lattice ice40
01:06 < fenn> in the 2000s there was a small academic effort at "reconfigurable computing" basically compiling your code as a region in the FPGA bitstream, and dynamically allocating/deallocating sections of gates like a heap in an OS. this was only possible on a single run of chips made for this purpose, because normally the entire bitstream has to be allocated all at once. there's no good reason for this
01:06 < fenn> requirement though
01:09 < fenn> ok AMD's website is giving me a headache
01:10 < fenn> now F4PGA supports not only ice40 but also xilinx 7-series and a few other "low cost" things i've never heard of
01:10 < fenn> is 7-series grunty enough to do anything useful with that we couldn't already do with the ice40?
01:11 < fenn> i get the impression the F4PGA website hasn't been updated in 5 years
01:14 < fenn> i think "1 bit" ternary LLMs could be implemented on FPGAs in a very straightforward way, but it would require either a huge number of gates or fast memory
01:16 < fenn> maybe the powers that be would be fine with a "read only" AI chip that had the model weights burned into silicon
01:26 < fenn> well i can't find recent numbers but virtex-7 had 50 million gate equivalents in 2013. for an LLM we'd need a few billion at least, probably a hundred billion, so that's a lot of chips
01:28 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has joined #hplusroadmap
01:28 < fenn> to train a gated neural network with this you'd need some alternative to gradient descent
01:34 < fenn> how does mythic not have an actual product after 15 years
01:50 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has quit [Remote host closed the connection]
01:50 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has joined #hplusroadmap
02:38 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has quit [Remote host closed the connection]
02:38 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has joined #hplusroadmap
04:21 < L29Ah> https://github.com/rkimoakbioinformatics/oakvar looks like a FOSS promethease
04:55 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has quit [Remote host closed the connection]
04:56 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has joined #hplusroadmap
05:18 < geneh2> I've seen some very encouraging results on analog electronics for running ML models. I've always though analog ML would require retraining on the dedicated hardware because of variation, but there appear to be ways to realize model weights on the analog hardware. None of the original training data is required
06:34 < nsh> nice
06:44 < kanzure> hmm https://www.getanyplant.com/plants?tag=Carnivorous
07:00 -!- etc-vi [~etc-vi@user/meow/girlchunks] has quit [Quit: nya]
07:00 -!- etc-vi [~etc-vi@user/meow/girlchunks] has joined #hplusroadmap
07:08 < hprmbridge> harmoniq.punk> I don't believe current ML architecture can benefit from analog power beyond the Mythic AI approach, because the information compression is very primitive with transformers. The redundancy is still too high when it does statistical encoding. Our biological neural net have lower redundancy because we infer new knowledge through analogies, while current ML architecture can not do this. In analog
07:08 < hprmbridge> harmoniq.punk> neural networks, the model will be stored as a tree in something like multiple-dimensional multiple-state SRAM cells. So it can uncompress instantly a certain state as a wave-function in an analog signal that modulate the input to get the output.
07:11 < hprmbridge> Lev> There's a lot of work on converting ANNs to SNNs since SNNs have historically had issues with training algorithms (i'm not up to date on modern solutions to this, but i'm pretty sure it's been somewhat addressed) and that's kinda half the work there, no?
07:13 < hprmbridge> harmoniq.punk> You can use nMigen(Python) or Chiesel(Scala) to generate the HDL code and then use manufacture tools to deploy the HDL code
07:14 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has quit [Quit: Wash your hands. Don't touch your face. Avoid fossil fuels and animal products. Have no/fewer children. Protest, elect sane politicians. Invest ecologically.]
07:14 < hprmbridge> harmoniq.punk> You can also look at OpenLane, Magic which are all open source.
07:14 < hprmbridge> Lev> If you use Yosys for any large designs expect to need a  lot of RAM
07:14 < hprmbridge> Lev> not that that's a surprise
07:14 < hprmbridge> harmoniq.punk> For analog I use Berkeley Analog Generator (BAG) 2.0
07:15 < hprmbridge> Lev> but i had relatively small circuits that yosys happily would eat > 64 gigs of ram to techmap
07:27 -!- justanotheruser [~justanoth@gateway/tor-sasl/justanotheruser] has quit [Ping timeout: 260 seconds]
07:30 -!- justanotheruser [~justanoth@gateway/tor-sasl/justanotheruser] has joined #hplusroadmap
07:31 < hprmbridge> harmoniq.punk> I use 256GB with AMD EPYC but I never used more than 100 for HDL projects but I never worked on big projects. Max OpenPower and RISC-V stuff. In analog you don't need so many resources
07:31 < hprmbridge> Lev> good point
07:31 < geneh2> @harmoniq.punk, it could use less power though
07:33 < hprmbridge> alonzoc> Lev. Don't mention yosys I don't want to be reminded of that abomination! You bought 256GB of RAM just to run it iirc
07:35 < hprmbridge> alonzoc> @Lev did you actually attempt to implement Knuth-Bendix for circuits or did you not in the end?
07:35 < hprmbridge> Lev> just 64
07:36 < hprmbridge> Lev> I ended up not doing KB and instead doing thermodynamic simulated annealing while caching large rewrite steps, remember?
07:38 < hprmbridge> alonzoc> I should really sit down and figure out that n-computad nonsense
07:39 < hprmbridge> Lev> Better you than me
07:46 < hprmbridge> harmoniq.punk> lol, no. I need for 3D stuff and physics simulation
07:49 < hprmbridge> harmoniq.punk> Doesn't compare with Cadence but you can do the job in the end and you don't necessarily to use
07:51 < hprmbridge> alonzoc> Yosys is sadly the only good open source game in town last time I checked and it does *work* so there's that
07:52 < hprmbridge> alonzoc> Tbh memory usage isn't the issue any good circuit optimisation system is gonna have whack RAM usage unless you're doing brute force search
07:53 < hprmbridge> Lev> I mean yes but yosys's memory usage is actively unnecessary on top of that
07:54 < hprmbridge> Lev> Like for some shit like it's subgraph iso routines there's simply no other way, but yosys just keeps a lot of extra data around for no real geod reason
07:54 < hprmbridge> Lev> Techmapping doesn't remove labels from previous maps, it just appends them
07:55 < hprmbridge> alonzoc> The fact subgraph iso is NP is the most disappointing CS fact to me
07:55 < hprmbridge> Lev> so now if you have a chain of transformations that generated 15 million and gates, expect 15 million copies of that transform chain as a string
07:56 < hprmbridge> alonzoc> Like graph isomorphism itself is *weird*
07:56 < hprmbridge> Lev> ig human readability but are we really expecting trivial human readability for meaningful circuit sizes to be a good decisios
08:00 -!- TMM [hp@amanda.tmm.cx] has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
08:00 -!- TMM [hp@amanda.tmm.cx] has joined #hplusroadmap
08:05 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has joined #hplusroadmap
08:36 -!- justanot1 [~justanoth@gateway/tor-sasl/justanotheruser] has joined #hplusroadmap
08:38 -!- justanotheruser [~justanoth@gateway/tor-sasl/justanotheruser] has quit [Ping timeout: 260 seconds]
09:57 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has quit [Quit: Wash your hands. Don't touch your face. Avoid fossil fuels and animal products. Have no/fewer children. Protest, elect sane politicians. Invest ecologically.]
10:03 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has joined #hplusroadmap
10:11 < hprmbridge> nmz787> I read up on that a lot when I came across it. We have a similar algorithm for dummy devices and our hermetic seal cell library.
11:10 -!- cthlolo [~lorogue@77.33.24.3.dhcp.fibianet.dk] has joined #hplusroadmap
11:26 -!- justanotheruser [~justanoth@gateway/tor-sasl/justanotheruser] has joined #hplusroadmap
11:29 -!- justanot1 [~justanoth@gateway/tor-sasl/justanotheruser] has quit [Ping timeout: 260 seconds]
11:50 -!- cthlolo [~lorogue@77.33.24.3.dhcp.fibianet.dk] has quit [Quit: Leaving]
16:28 -!- tinwhiskers [~tinwhiske@user/tinwhiskers] has quit [Quit: later]
16:32 -!- tinwhiskers [~tinwhiske@user/tinwhiskers] has joined #hplusroadmap
16:59 -!- darsie [~darsie@84-112-12-36.cable.dynamic.surfer.at] has quit [Ping timeout: 255 seconds]
20:33 -!- mxz__ [~mxz@user/mxz] has joined #hplusroadmap
20:34 -!- mxz [~mxz@user/mxz] has quit [Ping timeout: 240 seconds]
20:34 -!- mxz__ is now known as mxz
20:34 -!- mxz_ [~mxz@user/mxz] has quit [Ping timeout: 256 seconds]
21:48 -!- justanot1 [~justanoth@gateway/tor-sasl/justanotheruser] has joined #hplusroadmap
21:49 -!- justanotheruser [~justanoth@gateway/tor-sasl/justanotheruser] has quit [Ping timeout: 260 seconds]
22:24 -!- TMM [hp@amanda.tmm.cx] has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
22:25 -!- TMM [hp@amanda.tmm.cx] has joined #hplusroadmap
22:30 -!- Gooberpatrol66 [~Gooberpat@user/gooberpatrol66] has joined #hplusroadmap
22:36 < fenn> clumsy lobotomy is the goal of "center for AI safety", apparently https://assets-global.website-files.com/63fe96aeda6beab8f87d3023/65e8944051a65312012ecda0_concentric_circles.png
22:39 < fenn> supposedly just asking precise questions would be too dangerous
22:39 < fenn> so they want to nuke everything even remotely useful
22:40 -!- mxz_ [~mxz@user/mxz] has joined #hplusroadmap
22:55 -!- justanot1 [~justanoth@gateway/tor-sasl/justanotheruser] has quit [Ping timeout: 260 seconds]
22:59 < fenn> just add "security" to any word and suddenly it becomes nefarious harmful knowledge
23:00 -!- justanotheruser [~justanoth@gateway/tor-sasl/justanotheruser] has joined #hplusroadmap
--- Log closed Tue May 07 00:00:48 2024