• Intel’s newly-published 10-year manufacturing roadmap (AnandTech summary) projects a jump from 10 nm in 2019 to 1.4 nm in 2029, prompting skepticism about the credibility of the timeline given Intel’s recent history of repeated 10 nm delays.  
• Participants debated whether the move to 7 nm will actually be easier than 10 nm because of the introduction of EUV lithography, versus the counter-argument that EUV itself introduces new yield-killing shot-noise variability.  
• nmz787 highlighted that Intel’s public messaging omits the heterogeneous-integration strategy: digital logic may shrink, but analog and I/O blocks will stay on larger, optimized nodes and be combined via advanced packaging, improving overall yield.  
• The “chiplet revolution” was linked to Intel’s Foveros/EMIB-style 2.5-D and 3-D stacking, with references to IEEE Spectrum coverage explaining how small dies plus advanced interconnects can keep Moore’s-law-like scaling alive even if monolithic scaling stalls.  
• 2-D materials (e.g., transition-metal dichalcogenides) were noted as a possible path to sub-3 nm nodes, with the caveat that Intel’s material choices are ultimately driven by whatever maximizes revenue rather than any fixed technology commitment.  
• Competitive pressure from China’s SMIC and the broader Chinese semiconductor push (CSIS analysis linked) was raised as a wildcard that could erode Intel’s pricing power even if the technical roadmap is met.  
• A straw-poll estimate put the probability of Intel shipping 1.4 nm devices by 2029 at roughly 10 %, reflecting the channel’s overall pessimism about aggressive node-shrink promises.