- Open-source secure-element hardware is still missing: kanzure asked for public Verilog/VHDL implementations and concluded that “nobody makes any or knows how to make side-channel-resistant hardware anymore.”  
- Bluespec’s BSV high-level HDL toolchain is now open-source (github.com/B-Lang-org/bsc) and was described as “Haskell for RTL,” offering a formally-verified path to RISC-V SoC design.  
- Kami (github.com/sifive/Kami) and Clash (clash-lang.org, github.com/adamwalker/clash-riscv) were highlighted as additional open-source, type-safe hardware-description languages for CPU and peripheral development.  
- Discussion of Intel Optane/XPoint memristor technology: links to SemiAccurate articles showed mixed commercial success and questioned whether high-volume manufacturing and QC costs—not just blown fuses—explain pricing gaps.  
- HPE’s “The Machine” project and Gen-Z interconnect were reviewed; Gen-Z Linux support talk was shared (youtube.com/watch?v=MSCvkU0UKIU) as the latest public update on the memory-centric architecture effort.  
- Heterogeneous System Architecture (HSA) was debated via a 2017 Reddit thread asking if the initiative is “dead,” with links to AMD and cross-vendor CPU/GPU shared-memory specifications.  
- Samsung’s move to 5 nm mass production in Q2 2020 was noted, with L29Ah translating the node to “45 Si atoms wide,” underscoring the physical limits of further scaling.  
- NASA’s selection of commercial partners for Artemis human lunar landers was announced, signaling renewed heavy-lift and crewed-moon-mission development.