- A size-optimized, customizable 32-bit RISC-V soft-core CPU and SoC called NEORV32 was highlighted; it is written in platform-independent VHDL and includes an on-chip debugger compatible with the Minimal RISC-V Debug Specification v0.13.2, OpenOCD, and gdb.  
- Discussion centered on the practicality and security of Software Transactional Memory (STM), with participants noting that Intel’s hardware STM was disabled in firmware due to severe vulnerabilities and that no all-around good implementation has yet emerged.  
- Lock-free data structures were advocated as a near-zero-overhead alternative to STM; it was argued that teaching concurrency with toy examples rather than real practice hinders adoption of these simpler, faster techniques.  
- Near-memory transactional computing was proposed as a promising approach for whole-brain emulation and similar memory-intensive tasks, suggesting embedding circuitry in DRAM to reduce energy and latency.  
- Epic Games’ interest in STM was mentioned, with speculation that the company may have developed a better-than-state-of-the-art STM method to handle concurrency for large-scale real-time interactive simulations with millions of users.  
- A Nature paper on “In vivo partial reprogramming of myofibers promotes muscle regeneration by remodeling the stem cell niche” was shared, indicating ongoing interest in regenerative medicine and stem-cell niche engineering.