• Efabless/Google “ChipIgnite” shuttle now offers 130 nm SKY130 open-PDK fabrication: 10 mm² user area, 100 QFN or 300 WCSP parts for US$9 750, or 1 000 WCSP parts for US$20 k, with only a US$200 deposit and no open-source licensing requirement.  
• Libre-SoC project is migrating from 180 nm IMEC MPWs to 130 nm SKY130; at 130 nm a 10 mm² die can hold ~2 M transistors, still tight for a 64-bit Power ISA core plus caches, so the HDL remains node-agnostic.  
• All Google-sponsored shuttles embed a fixed RISC-V “Management Core” that limits raw pad access to ~60 MHz and complicates analog designs; a separate analog shuttle without the core exists for mixed-signal work.  
• SkyWater 130 nm PDK and cell libraries are fully open-source (GitHub, GoogleSource, ReadTheDocs), but documentation for seal/guard-ring and frame abutment is still missing.  
• Vertical-First Vectorisation (SVP64 extension to Power ISA) treats the ISA as a software API for a vector unit, achieving 4.5× code-size reduction versus traditional SIMD and promising large energy savings, though exact pJ/instruction figures are unmeasured.  
• Remote RTL co-simulation workflow shared: SystemVerilog DPI plus C/Python bridges enable real-time JTAG and network I/O for pre-silicon validation; DDR3 training simulations complete in 5–10 min on Icarus Verilog using Micron’s digital models.  
• Xilinx open-sourced the Vitis HLS front-end (LLVM-IR → FPGA), sparking interest in an Emscripten/WebAssembly/LLVM-to-ASIC pipeline and in FPGA-based “ICE” boards that emulate future ASICs while driving real peripherals.  
• Wishbone vs. AXI4/TileLink debate: Wishbone is a simple “contract of sale” bus adequate for basic SoCs but insufficient for cache-coherent designs without extra layers.  
• New paper “vSGX: Virtualizing SGX Enclaves on AMD SEV” shared as a route to run Intel SGX workloads on AMD hardware, expanding trusted-execution options for open hardware projects.  
• Two open-source HDL toolkits highlighted: hwt (Python/C++ VHDL/Verilog/SystemC generator and simulator API) and hwtHls (LLVM-based high-level-synthesis library built on hwt for rapid hardware development).