# Summary of IRC Log from #hplusroadmap (Dec 8, 2016)

* A discussion about FPGA development took place, with recommendations to learn both VHDL and Verilog, and a suggestion to start with MyHDL in Python which can emit both languages.

* Participants discussed verification methodologies for hardware description languages, including Open Verification Methodology (OVM), which provides random number/bit generators to test HDL components and verify correctness.

* The conversation touched on formal verification techniques versus testing all permutations, noting that theorem provers are important for verifying correctness in Verilog as testing all possible states is impractical.

* A link was shared to edaplayground.com, which offers various HDL simulation backends including commercial options that can be used for non-commercial work.

* A video lecture titled "Stochastic Models in Robotics" by Gregory S. Chirikjian was shared in the channel.

* Time magazine's recognition of CRISPR as a runner-up for Person of the Year 2016 was mentioned with a link to the article.