Webpage: Dr. Lynn Fuller
email:
Lynn.Fuller@rit.edu
Notes on RIT CMOS Processes, Testing and Design
RIT is supporting two different CMOS process technologies. The older p-well CMOS and SMFL-CMOS have been phased out. The SUB-CMOS process is used for standard 5 Volt Digital and Analog integrated circuits. This is the technology of choice for teaching circuit design and fabricating CMOS circuits at RIT. The ADV-CMOS process is intended to introduce our students to process technology that is close to industry state-of-the-art. The ADV-CMOS process is used to build test structures and develop new process technologies at RIT.
RIT p-well CMOS Lambda = 4 µm, Lmin = 8 µm (no
longer supported)
RIT SMFL-CMOS Lambda = 1 µm, Lmin = 2 µm (being phased
out)
RIT Subµ-CMOS Lambda = 0.5 µm, Lmin = 1.0 µm, Leff <
1.0um
RIT Advanced-CMOS Lambda = 0.25 µm, Lmin = 0.5 µm, Leff ~0.30um
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Processes | ||
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Testing | ||
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CMOSTEST.pdf FAC SUB.DAT TestResults.ppt CMOS IC Test.pdf |
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PMOS_TEST_DATA.xls |
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CMOSTEST.pdf Parameter Extractor.xls |
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SPICE Parameters | ||
Intro to LTSPICE Video RIT SPICE Models |
Intro to LTSPICE.wmv LTSPICE MODELS.txt |
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SPICE MOSFET Model Calculator |
SPICE Parameter Calc.XLS |
SPICE MOSFET Models |
SPICE Examples More SPICE Examples |
SPICE EXAMPLES.pdf More SPICE EXMPLES.pdf |
SPICE Examples More SPICE Examples |
Design | ||
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